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v3.3.5
Series of meetings devoted to the design of the OBELIX sensor for the VTX proposal.
Connection link: https://speakapp.link/to/ItwHIA
There is now a chatline for discussion on OBELIX:
https://chat.belle2.org/channel/vtx_upgrade_obelix
* Carlos on L1+L2 module concept = iVTX
- current assumption for VTX: stick to current VXD volume
-> we know already other constraint might arise, but to be considered later
- all silicon concept
o silicon frame support 4 sensors (cut out as one piece from the wafers)
=> note 4 sensors over the required length (123mm) implies sensor length ~30 mm
o redistribution layer (RDL) on top of the sensors brings power/data to 4 chips
- cabling and service only in BWD side
- computation for power distribution redistribution layer
o with Cu traces possible optimum for section: 3 um x 1.8 mm
o additional power dissipation from power resistivity ~20 mW/cm2
- sensor width (r/phi direction) considerations
o #reticules per wafer tends to prefer 19 mm total sensor width over 17 mm
o other constraints will be integratd in further discussions
- material budget estimate
o sensor + metal traces ~ 0.07 % X0
o overlap to be taken into account for a lore refined number
- Questions discussed
o Impact of photons absorbed in the 3 um thick Cu redistribution layer?
=> need to do some computation
o When is the RDL done?
=> could be done at post-process level but on wafer (before chip dicing)
* Massimo on L3-L5 module concept = oVTX
- assumption 2 FPCs will connect each half of the sensors on the ladder
o longest for L5 (69 cm), one FPC serves 11 sensors over 36 cm
- two options considered, global power rails or multiline bus
o pros and cons discussed, multiline option considered further
- FPC material budget computed for relative standard techno with 2 metal layers
o assumption for metal thickness: allow for 100 mV maximum voltage drop
o For layer5, the estimates are for Cu ~0.176 % X0 and for Al ~0.083 % X0
o For the shorter layer3-4; the budget is around to 0.1 %X0 (Cu) and 0.6 %X0 (Al)
- To go beyond, a number of inputs are missing, like:
o nb of data lines and electrical requirements
o need VDD, GND pad location on the sensor gross layout
o breakout of power consumption (analogue vs digital) and dependence on occupancy
o need for additional components
- Questions discussed
o Need to include the power loss into the LDO (200 mV drop)
=> probably 220 mW/cm2
o Maybe consider asymmetric flex to limit the material budget where most particles are (FWD)
=> possibly a second order optimization
o Power drop will depend on the sensor position
* Tomek on some OBELIX options
- propose prototyping to test RDL at wafer level (with IZM)
o require existing wafer with sensors
o call to the community for availability
- initial discussion on bonding thin sensors on silicon-frames
o option 1: thin the frame then flib-chip
o option 2: glue+wire-bond sensor to frame then thin the frame
- many metal options in TJ kit
o to be checked directly with foundry
- arrangements of padring, especially for powering
o current TJ-Monopix2 has padring over 3-sides, is it practical for module integration?
o preferred top-bottom arrangement will have impacts thresholds and requires careful metal line new layout in pixel matrix
* About OBELIX collaboration, Tomek & Jerome
- current situation is neither well structured nor clear with respects to timeline, money and validation by support institutes
o we target a first version of OBELIX sometime in 2022
o strategy is to gather interest and clarify the plan together
- need some kind of "legal" agreement between contributors, especially before sharing any layout of the existing Monopix2
o MOU could be a good way
o C.Irmler: in RD50, each institute need signing with all other institutes
o J.Dingfelder: reaching sign-off all parties could take half a year
=> no real conclusion during the meeting, the matter will be discussed at the forthcoming steering meeting
- An initial task-group association list was established -> to be refined
* Statement of interest from groups present at the meeting
NOTE 1: of course, all numbers below are still indicative
NOTE 2: the people listed below is not necessarily fully for OBELIX design
- Uni.Bonn: 4 designers (incl. 1 PhD student) + 1 post-doc (to be hired) + 2 PIs ~2 to 3 FTEs
test -> main test site for Monopix2
design -> integration, digital logic, verification
- HEPHY: ~0.8 FTE share among 6 people (including 1 PhD student and 1 post-doc)
design -> digital part, verification and connection to DAQ
test -> both Monopix2 and OBELIX
- CPPM: team of ~6people, corresponds to ~1.5 FTE for tests, ~1.5 FTE for design
test -> currently on Monopix series
design -> LDO, SEE structures, analogue front-end, DACs, integration & verification
LDO, SEE, FEE, DACs
- Bergamo/Pavia: 4 experienced people, additional PhD/post-doc to expect
design -> analogue front-end & analogue support
- Uni.Barcelona: ~1 FTE (1 senior + 1 PhD student)
design -> analog & digital design contributions
- Additional interest by Valencia mentioned by Carlos -> to follow
- IPHC: about 4 designers, supervision by 2 PI (designer+physics) ~2 FTE for now, ~3 later
design -> analogue front-end, pixel matrix integration, contribution to digital, verification
test -> not yet there, but willing
- Pisa: working on module integration
- IJClab: working on mechanics for 2022 and planning to do so for 2026
- KEK: currently focused on DUTIP, observer status
* Time for next meeting
- we decided to set-up a poll for choosing a VTX weekly time-slot,
where we will discuss in turn various topics (sensor, integration, ...) somewhat in details
==>Link to poll: https://www.when2meet.com/?11885006-YxDL7